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Figure 6: Discriminator Schematic

The discriminator schematic is shown in Figure 6. The circuit is a high-gain differential pair M1/M2 with diode-connected loads M3/M4 and tail (bias) current provided from an external input via a 1:1 mirror M5/M5A. Miller capacitance in M1/M2 is reduced by cascode devices M1C/M2C. Symmetrical class A/B output stages are provided using two sets of current mirrors. Positive feedback is provided via two inverters (M16/M17 and M18/M19) and a second differential pair (M1A/M2A). The amount of hysteresis may be programmed externally via mirror M5/M5A. A primary design goal was to achieve a completely symmetrical design (in both circuit topology and layout) to minimize input offsets.

The discriminator performance is summarized in Table 2.

Table 2: Discriminator Performance

A key performance characteristic is time walk. The propagation delay through the discriminator varies with pulse amplitude due to two factors, time walk and time slewing. Time walk refers to the inherent variation in delay of the discriminator itself; it is measured with a step-function input pulse at the discriminator input. The 600pS quoted above corresponds to a range of input signals from about 20-200 primary electrons above a threshold of 20 primary electronics. This is quite good. However, time slewing also occurs because of the 15ns peaking time of the shaper; thus the effective time walk is significantly longer. If this is proves to be a problem, there are two possible solutions: offline correction using an ADC, and automatic correction using a controllable delay line. The latter technique has been successfully prototyped by others[5] and warrants further study.

Eric Hazen
Thu Oct 10 18:19:00 METDST 1996