ATLAS MDT Mezzanine Board Updated 10 July 2003, hazen@bu.edu BACK to BMC page Please see PAGE AT HARVARD maintained by John Oliver for current production information. ...or see this replacement page since the Harvard one seems to be dead!

Older Information

Mezzanine "LITE" Documentation

See Also:

For Rome 4x6 version See E.Spiriti Page

also see Readout Overview Page

and Hedgehog Page

Mezz_Lite_JK_11Apr01.pdf Mezz_Lite_JK_11Apr01.doc

E. Hazen

11 April 2001

Connectors and Pinouts for 3x8 Mezz Lite

Threshold Circuit Operation: There seems to be much mystery surrounding the correct operation of the threshold circuit. Here is a short presentation which should clear things up.

Documentation for Specific Revisions

Documentation for 4x6 Rev 1.1 on separate page here.

Documentation for Rev K on separate page here.

Documentation for Rev J on separate page here.

Documentation for Rev H

Revision H has been prototyped (September 2000).
Significant changes:

• Switch to AMT-1 TDC.
• Change to VQ44 package for Xilinx
• Move all digital circuitry to TDC end and shrink board outline

OrCAD files	MEZZH.DSN MEZZH.MAX	Schematic Layout
Schematic (PDF)	sch_top.pdf	(4 pages)
Gerbers	mezzH.zip
Assembly docs	revH_assy.pdf

There is already one known problem with this design: The Xilinx pinout is completely wrong, so it must be removed from the JTAG chain for the board to work at all.

Documentation for Rev G

Revision G has been prototyped (August 2000).
Significant changes:

• Add 36-pin mini-D-ribbon connector with all external connections. All other connectors (except header for Xilinx prototyping) are removed.
• Increase board with on top edge by about 1cm to accomodate connector. Route digital power and signals from left to right across the top outside the original board outline to avoid digital-analog crosstalk.

OrCAD files	MEZZG.DSN MEZZG.MAX	Schematic Layout
Gerbers	mezz-g.zip
Schematic (PDF)	MezzG_top.pdf	All but first sheet are same as Rev E-F
Component list	COMPS.pdf or COMPS.xls
Assembly docs	top_assy.pdf bot_assy.pdf prot.pdf

Documentation for Rev F

Revision F is being produced (qty 10) in July 2000.
Significant changes:

• Change from 4 to 6 layers, add analog gnd on bottom
• connect right and left digital sections with inner layer traces only
• Add floating "shield" layers around digitial section
• Fix threshold op-amp oscillation (series Rs)
• Move hedgehog standoff holes 0.050 in right
• Increase power plane isoloations to 0.1 in

OrCAD files	MEZZF.DSN MEZZF.MAX	Schematic Layout
Gerbers	gerberF.zip

Documentation for Rev E

Revision E was produced (qty 10) in June 2000. No more will be produced until Revision F. Significant changes (see slides ) with pictures):

• Board is 8mm narrower to fit with patch panel
• RJ-45 connectors switched to 2mm vertical headers
• Digital power added to TDC data cable
• Optional shield connection (R-C to GND) added to all cables
• All connectors moved to center of board to avoid patch panel conflicts

Reference	ref_RevE.pdf ref_RevE.gif	Photo with connector locations
Schematics	MezzE_sch.pdf	As built 9 Jun 2000
Connector Pinouts	RevE_pinout.txt	Pinout of new 2mm connectors
Protection Circuit	prot.pdf	Details of protection circuit layout
Gerber Files	gerber.zip
OrCAD Files	MEZZE.DSN MEZZ4_E.MAX	Schematic Layout

Documentation for Rev C & D

Revision C was produced (only a few) in early 1999.

Revision D was produced in October 1999. 10 boards were built of which about 5 were functional, and used for testing at Boston and Michigan.

Schematics	mezz_d_built.pdf (841kb) Corrected to Rev D - 19 Apr 2000
JTAG Information	The board has a JTAG chain consisting of two devices. In order from "JTAG in" to "JTAG out" connectors:   AMT-0 TDC   Xilinx chip   JTAG (programming examples)
Photos	Top view: Top.PDF Bottom view: Bottom.PDF
Connectors	Jumpers/Connectors detailed pinouts
Gerber files	RevD_gerber.zip