Mezz Lite Rev J

Maintained by E. Hazen hazen@bu.edu.
Updated 4 April 2001

Here is some documentation on ATLAS mezzanine lite Rev J.

ECOs:

Omit JP16, JP18, JP20 (SMT jumpers)
Install SP6, SP9 (thru-hole jumpers)
Change R2 from 100k to 10k

Notable changes since Rev H:

Add missing AMT-1 power pins: (144->Vdd) (136->GND)
Fix AMT-1 TDC Wiring mistakes:
Tie to GND: RA0-4, GETDATA, WR, CS, DSPACE
Tie to Vdd: START
Fix Xilinx FPGA pinout
Tie LVDS driver enables (U10 pins 4, 12) to Vdd
Change board dimensions again. Back to "original" 92mm height to fit on barrel chambers.
Re-do placement at digital end

Schematic	mezzJ_sch.pdf (PDF) MEZZJ.DSN (OrCAD)
Layout	mezzJ_slide.pdf (Slide) mezzJ_gerbers.pdf" (Layers) MezzJ.max (OrCAD)
Gerber data	mezzj.zip
Mechanical Drawing	hh_mezzj.pdf (PDF) HH_MEZZJ.dxf (AutoCAD)
Assembly documents (parts list etc)	assy.zip
Solder Paste Masks	MEZZJ.SPT (top) MEZZJ.SPB (bottom)

Here are some screen images of the layout:

revj_top.jpg PCB photo (top)
revj_bot.jpg PCB photo (bottom)
top.GIF Top layer
inner.GIF Inner signal layer (digital Vdd)
bot.GIF Bottom layer
shield.GIF AGND / SHIELD

	revj_top.jpg	PCB photo (top)
	revj_bot.jpg	PCB photo (bottom)
	top.GIF	Top layer
	inner.GIF	Inner signal layer (digital Vdd)
	bot.GIF	Bottom layer
	shield.GIF	AGND / SHIELD