Here are a few notes on JTAG programming for the Rev C ATLAS mezzanine
boards.  (update 5 Oct 1999)

CONNECTORS

  There are two RJ-45 connectors on the board labelled JTAG IN and JTAG OUT.
  On Rev C boards they have incompatible pinouts (this will be fixed in
  Rev D so that both match the JTAG OUT given below):

    JTAG IN:                          JTAG OUT:
		    
         1  TDI-     5  TMS+              1  TDO+      5  TMS-
         2  TDI+     6  TCK-              2  TDO-      6  TCK-
		  				   
         3  TCK+     7  /TRST+            3  TCK+      7  /TRST+
         4  TMS-     8  /TRST-            4  TMS+      8  /TRST-

  A cable is usually supplied with Rev C boards to "fix" the input
  pinout.


JTAG CHAIN

  JTAG IN --> TDC --> Xilinx --> JTAG out


PROGRAMMING EXAMPLES

  The TDC instruction register (IR) is 4 bits long plus 1 parity bit.
  THe XIlinx IR is 4 bits long with no parity.  In all examples below
  binary data is written in order received or transmitted, left-to-right.

  Example 1:  Read TDC ID code

    Send IR = 1111 1000 0
                        ^  TDC Parity
                   ^^^^    TDC instruction "IDCODE"
              ^^^^         Xilinx instruction "BYPASS"

    Send DR = (more than 32-bits of "don't care")
    Should receive TDC ID = 1111 0001 0000 0011 0101 1011 0000 0001


  Example 2:  Set Threshold DAC

    Send IR = 0010 1111 1
                        ^  TDC Parity
                   ^^^^    TDC instruction "BYPASS"
              ^^^^         Xilinx instruction "LOADDAC"

    Send DR = 00001010 10000000
                       ^^^^^^^^  binary DAC value = $80 (note bit order)
              ^^^^^^^^           control word for MAX550A DAC


    DAC value    Output Voltage on JP4 pin 3 (remove jumper)
      $00          0V
      $80	   1.65V (Vdd/2)
      $FF	   3.3V